The present disclosure relates to a semiconductor device and a manufacturing method thereof, which is formed from a package which includes a semiconductor chip.
In an electronic apparatus, a so-called PoP (Package on Package) structure is proposed (for example, refer to Pamphlet of International Publication No. WO 2006-082620 in FIG. 1) in which a plurality of packages including a semiconductor chip is laminated, in order to realize miniaturization of components which use a semiconductor chip.
In the PoP structure, it has an advantage in which an area for mounting is reduced and a transmission path is short, compared to a structure in which a plurality of packages is aligned horizontally.
In a PoP structure in the related art, connection between a lower package and an upper package is performed using solder balls or a wiring which is provided at the periphery of the semiconductor chip of the lower package.
In this configuration, the upper package is necessary to be formed to a large size to correspond to a connection portion of the solder ball, or the like.